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PRO-LINX TM GS7005
Complete Serial Digital Video Receiver
DATA SHEET FEATURES * SMPTE 259M-C compliant * fully integrated 270 Mb/s SDI receiver * integrated cable equalization (100m Belden 8281 typical) * low power consumption (750mW typical) * operates from 0C to 85C * small footprint with minimal external components * Lock and Carrier Detect output indications * H timing signal output * SMPTE descrambler and NRZI decoder may be disabled for DVB - ASI applications * ease of design use and adjustment free operation ORDERING INFORMATION APPLICATIONS Limited space, low power SMPTE 259M-C or generic 270Mb/s serial to parallel interfaces; DVB-ASI 270Mb/s receive interface; broadcast quality uncompressed video interface for industrial and professional video equipment such as video editing workstations.
PART NUMBER GS7005 - CQT GS7005 - CTT PACKAGE 52 pin MQFP 52 pin MQFP Tape TEMPERATURE 0C to 85C 0C to 85C
DESCRIPTION The GS7005 is a BiCMOS integrated circuit capable of operating as a complete 270Mb/s Serial Digital Video receiver. The GS7005 provides a complete serial digital video receive solution while consuming only 750mW. The serial data input accepts SMPTE 259M-C compliant signals. An on-chip by-passable equalizer typically provides 100m of co-axial cable equalization. The clock recovery is performed on chip with minimal external components. The incoming serial data is decoded using an NRZI decoder and SMPTE descrambler to provide SMPTE 125M compliant 27Mb/s parallel data outputs and clock.
GS7005
C1 C2
LOCK CD
SIGNAL LOCK DETECT
PLL
f/10 PCLKOUT H
MUX
TRS DETECTOR SDI SDI EQUALIZER SLICER NRZI DECODER DESCRAMBLER
S to P 10
DOUT[9:0}
EQ
SMPTE
BLOCK DIAGRAM
Revision Date: January 2001 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com
Document No. 522 - 14 - 06
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Range (any input) DC Input Current (any one input) Power Dissipation (VCC = 5.25V) Maximum Die Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (soldering 10s) VALUE 5.5V GND < VIN < VCC 10mA
GS7005
1W 125C 0C <= TA <= 85C -65C <= TS <= 150C 260C
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, TA = 25C, unless otherwise specified. Serial data rate = 270Mb/s, Parallel Data Rate = 27Mb/s, PCLK = 27MHz
PARAMETER Positive Supply Voltage
SYMBOL VCC P ICC VIL VIH VOL VOH
CONDITIONS Operating range VCC = 5.25V VCC = 5.25V VCC = 5.25V VCC = 4.75V VCC = 5.25V VCC = 4.75V
MIN 4.75
TYP 5.00
MAX 5.25
UNITS V
NOTES
TEST LEVEL 6
Power Consumption Supply Current Logic Inputs - Low Logic Inputs - High Logic Outputs - Low Logic Outputs - High TEST LEVELS
2 2.4
750 140 -
0.8 0.5 -
mW mA V V V V
5 1 6 6 1 1
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product.
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AC ELECTRICAL CHARACTERISTICS
VCC = 5V, TA = 25C, unless otherwise specified in `conditions' Serial data rate = 270Mb/s, Parallel Data Rate = 27Mb/s, PCLK = 27MHz
PARAMETER Parallel Data - Rise/Fall Time PCLK Rising Edge to DOUT(N) Centre PCLK Rise/Fall Time Input Return Loss
SYMBOL tR/F_DOUT tD tR/F_PCLKOUT LOSSIN
CONDITIONS CL = 20pF
MIN 1.0 -
TYP 17
MAX 6.0 5 3.0 -
UNITS ns ns ns dB
NOTE S 1 2, 3 1
TEST LEVEL 4, 7 4, 7 4, 7 7
GS7005
CL = 20pF 75 match 5MHz to 270MHz
0.5 -
Asynchronous Lock Time Synchronous Lock Time Input Jitter Tolerance Output PCLK Jitter
tLOCK_ASYNC tLOCK_SYNC tJ_SI tJ_PCLKOUT Pathological Input Pseudorandom Input Pathological Input
-
0.35 800
250 10 -
ms s U.I. ps p-p
4 5 6
1 1 7 1
-
1000 100
-
ps p-p m
6
7 7
Error Free Cable Length
Pseudorandom Input Pathological Input
75
100
-
m
6, 7
1
NOTES 1. Rise/Fall time is defined as the time for the signal to rise from 20% to 80% of the specified p-p value, or to fall from 80% to 20% of the specified value. 2. Refer also to Figure 10. 3. This is the time difference between the rising edge of PCLKOUT and the centre of the bit period. 4. This is the time delay between a valid serial TRS signal on the input to the moment valid data appears on the parallel outputs. 5. This is the time for the PLL to re-lock when video streams are switched during the vertical blanking interval in accordance with SMPTE RP168-1993. The two streams may be 180 out of phase with respect to one another, but pixel aligned. 6. This pathological pattern is defined in SMPTE RP178-1996, paragraphs 4.1 and 4.3. 7. "Error free" is defined as no single bit errors over a period of 10 minutes, using Belden 8281 Cable and 75 connections. The MIN value is fully tested and the TYP value is based on using the EB7005 Evaluation Board. TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product.
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TEST SETUP
DATA TEKTRONIX GigaBERT 1400 TRANSMITTER DATA GS9028 CABLE DRIVER
BELDEN 8281 CABLE
GS7005
EB7005 BOARD
TEKTRONIX TDS 820 SCOPE
CLOCK TRIGGER
Fig. 1a Test Setup for Jitter Measurements
TEKTRONIX VIDEO SlGNAL GENERATOR
VIDEO STREAM WITH EDH
BELDEN 8281 CABLE
EB7005 BOARD
EB9021 EDH ERROR COUNTER
Fig. 1b Test Setup for Error-Free Cable Length
HP 4195A NETWORK ANALYSER
BELDEN 8281 CABLE
EB7005 BOARD
Fig. 1c Test Setup for Return Loss Measurements
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PIN CONNECTIONS
GND GND RSVD1 RSVD1 VCC3 CD SMPTE RSVD0 RSVD0 PCLKOUT VDD GND GND 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 GS7005 6 TOP VIEW 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 GND GND C1 C2 VCC1 SDI SDI VCC2 RSVD0 GND EQ RSVD1 GND 39 38 37 36 35 34 33 32 31 30 29 28 27
GND RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 H GND
GND DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 LOCK GND
GS7005
NOTE: RSVD = Reserved
PIN DESCRIPTIONS
NUMBER 1, 13, 14, 26, 27, 39, 40, 52 2-11, 22, 44, 45 12 15 16, 17 18 19, 20 21 23 24 25, 49, 50 28 29-38 41 42 43 46 SYMBOL GND RSVD0 H GND C1, C2 VCC1 SDI, SDI VCC2 GND EQ RSVD1 LOCK DOUT[9:0] GND VDD PCLKOUT SMPTE TYPE O I I O O O I Connect to Ground. Connect to Ground. H Indication. HIGH after EAV ID and LOW after SAV ID. Ground for analog blocks of the device. External 100nF loop filter capacitor connection. Power supply for analog blocks of the device. Differential Serial Data Input Power supply for PECL blocks of the device. Ground for PECL blocks of the device. Equalizer Control; LOW = EQ on, HIGH = EQ bypassed. Connect to VCC. Signal Lock Indication Output. Goes HIGH approximately 38s after valid parallel data occurs. 27Mb/s Parallel Data Outputs. Ground for CMOS blocks of the device. Power supply for CMOS blocks of the device. 27MHz Clock Output. NRZI decoding and descrambling control. LOW = NRZI and SMPTE mode on. HIGH = NRZI and SMPTE mode disabled. 47 48 51 CD VCC3 GND O Carrier Detect. Active LOW. Goes LOW when carrier is detected and high when carrier is lost. Power supply for Analog and PECL blocks of the device. Ground for analog and PECL blocks of the device. DESCRIPTION
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INPUT / OUTPUT CIRCUITS
VDD
ESD
GS7005
IN
TO INTERNAL STRUCTURES
GND
Fig. 2 SDI, SDI
VDD
ESD
TO INTERNAL STRUCTURES
OUT
GND
Fig. 3 DOUT[9:0], H, LOCK, CD, PCLKOUT
VDD
ESD
TTL-IN
TO INTERNAL STRUCTURES
GND
Fig. 4 EQ, SMPTE
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TYPICAL PERFORMANCE CURVES (VCC = 5V, TA = 25C unless otherwise shown)
J1
0
J2 J0.5
-10
RETURN LOSS (dB)
270MHz
GS7005
-20 54MHz -30 135MHz 1.97GHz 270MHz 540MHz -40
-50 0.05 GHz 1 GHz
Impedances normalized to 509 FREQUENCY (GHz)
-J0.5 -J2 -J1
Fig. 5 Input Return Loss
Fig. 7 Input Impedance
800 700 0 600
AMPLITUDE (dB)
POWER (mW)
500 400 300 200
600kHz -3
-6 100 0 1k 10k 100k 1M 10M 0 10 20 30 40 50 60 70 80 90
FREQUENCY (Hz)
TEMPERATURE (C)
Fig. 6 Loop Bandwidth
Fig. 8 Power vs. Temperature
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RECEIVER OPERATION
EQ 0 1 0 1 SMPTE 0 0 1 1 GS7005 Operating mode SMPTE 259M Receiver (Equalizer ON, SMPTE / NRZI Descrambler enabled). SMPTE 259M Receiver with equalizer bypassed. Receiver function with equalizer enabled and NRZI and SMPTE Descrambler disabled.
GS7005
Receiver function with equalizer bypassed and NRZI and SMPTE Descrambler disabled.
The output of the LOCK pin is logic high approximately 38s after the receiver has successfully locked to the input serial bit stream. The output H is set low after the SAV ID and is set high after the EAV ID when these sequences are identified in the incoming bit stream.
If external equalization is performed prior to this device, bypass the equalization control function (EQ) by setting it HIGH. To turn off the NRZI and SMPTE Descrambler function, set SMPTE HIGH. When operating in this mode, the output of H is either "1" or "0" (indeterminate).
DIAGRAMS The figure below shows the timing relationship between the outputs of the GS7005.
PCLKOUT DOUT[9:0] H
... XXX XXX 3FF 000 000 SAV ID XXX XXX XXX ... XXX ...
XXX
XXX
3FF
000
000
EAV ID
XXX
XXX
Fig. 9 Timing Diagram for Parallel Outputs, PCLKOUT, and H
The figure below shows the relationship between the parallel clock and the parallel data outputs. The rising edge of the parallel clock is within 5ns of the centre of the data.
WORD CENTRE 5ns 5ns
DOUT[9:0]
PCLKOUT
Fig. 10 Parallel Clock Alignment
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DETAILED DESCRIPTION The main functional blocks of the GS7005 are: 1. PECL input buffer 2. Fixed Gain Equalizer 3. Slicer 4. NRZI Decoder & SMPTE Descrambler 5. TRS Detector 6. Signal Lock Detect 7. Serial to Parallel Convertor
signal by applying the same algorithm to the received signal. For data structures that do not require descrambling and NRZI-NRZ conversion, bypass this block by setting the SMPTE pin to logic HIGH.
5. PLL, MUX and f/10
The PLL clock recovery circuitry provides an internal, synchronous 270MHz clock. The 27MHz parallel data clock is derived from the serial clock through a resettable frequency divider. To synchronize the parallel clock signal, set the frequency divider to the initial state at the same time the state machine has detected the Timing Reference Signal (TRS). The PLL self-centres the VCO to approximately 29MHz when there are no input data transitions. This allows the PLL to lock when a valid signal within the lock range is applied. However, if the GS7005 detects a spurious input with random data transitions, the centering function of the VCO is inhibited. This causes the VCO control voltage to drift to a low clamp level resulting in a VCO frequency of 22MHz. To prevent this "latch-up" condition implementation of a high impedance (1M) bleed resistor across the C1 and C2 (loop filter, pins 16 and 17) is recommended. Due to the large resistance value, the effect on IJT is negligible (see Figure 11).
6. TRS DETECTOR
GS7005
Refer to the Functional Block Diagram on the front page of this data sheet.
1. PECL INPUT BUFFER
This differential input buffer features a built-in load termination for the incoming SDI signal. The load is characterized as 75 over a wide frequency range and is made up of an internal fixed resistor and current source.
2. FIXED GAIN EQUALIZER
The Fixed Gain Equalizer stage is used to compensate the frequency dependent loss of the SDI signal through co-axial cable. The SDI signal is connected to the input pins (SDI/ SDI) either differentially or single ended. The input signal passes through a fixed gain equalizing stage whose frequency response closely matches the inverse cable loss characteristic. The equalizer typically provides 100m of coaxial cable equalization. The frequency response is optimized for maximum cable length. For short cable lengths (<10m), bypass the equalizing stage by setting the EQ control pin to a logic HIGH level. If an external equalizer is used, bypass the internal equalizer of the GS7005 to avoid over-equalization (see Figure 12).
3. POST EQUALIZATION SLICER
The TRS Detector detects the TRS headers (EAV and SAV). It consists of a word-counter, bit-counter and control statemachine. The bit-counter is reset by either the decoded data or the output of the state-machine. In a normal case, the state-machine output is LOW. The reset of the bit counter is active LOW so that the bit-counter will be started when the data is HIGH. The detection of a valid TRS header is indicated by a level change of the H-signal pin.
7. SIGNAL LOCK DETECT
The Post Equalization Slicer stage slices the equalized signal, thereby eliminating any DC offset due to the AC coupling requirement of the SDI signal. Using a differential comparator, the received signal voltage is compared to a midway voltage, known as the baseline or the slicing level. The sliced signal is then applied to the NRZI/SMPTE Decoder/Descrambler and the PLL MUX.
4. NRZI DECODER & SMPTE DESCRAMBLER
When there are no input data transitions, the CD pin goes to a HIGH logic level and forces the VCO to the centre frequency as described in section 5, PLL, MUX, and f/10. This output can be used to control an external transistor and LED. When there are input data transitions (valid or invalid), the CD pins goes to a LOW logic state. The locking state of the PLL is indicated by the output LOCK signal being set to a logical HIGH level. This pin however, may have periodic transitions to a LOW logic state of 64s maximum duration even though the device is properly locked. The parallel data signal integrity is not affected under these conditions. Therefore, the LOCK pin should not be used as a logic control signal if a steady level is required. The output voltage remains in a logic HIGH state for a sufficient period and can be used to drive visual indicators such as LEDs.
To comply with the the ANSI/SMPTE 259M standard, use a scrambled, polarity free NRZI code. The polynomial 9 4 generator for the scrambler is G1(X) = X +X +1. The NRZI code is produced by a second polynomial, G2(X) = X+1. The NRZI Decoder and SMPTE Descrambler blocks within the GS7005 regenerate the original NRZ unscrambled
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8. SERIAL TO PARALLEL CONVERTOR
The final function of the GS7005 is the serial-to-parallel conversion. The output signals of the receiver are ten data signals and one clock signal. The shift register is filled by the serial data and read out at a positive edge of the readout signal. After parallel read out of the shift register, the parallel data is sampled with the negative edge of the 27MHz clock to achieve synchronization.
GS7005
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APPLICATION CIRCUITS
VCC 220 10k CD 100n VCC MODE VCC 100n 10p
100n 10
VCC 33
VCC VCC
GS7005
52 51 50 49 48 47 46 45 44 43 42 41 40 PCLKOUT RSVD1 RSVD1 VCC3 GND GND VDD GND RSVD0 SMPTE RSVD0 GND CD 1 2 3 4 5 6 7 8 9 10 11 12 13 PARALLEL CLOCK OUT
GND
RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 GS7005
RSVD1
H VCC1 VCC2 GND GND SDI SDI C1 C2 GND
GND
GND
14 15 16 17 18 19 20 21 22 23 24 25 26 100n 100n 100n VCC VCC 10 10 EQ VCC
RSVD = Reserved. All resistors in ohms, all capacitors in farads, unless otherwise shown.
EQ
GND 39 DOUT0 38 DOUT1 37 DOUT2 36 DOUT3 35 DOUT4 34 DOUT5 33 DOUT6 32 DOUT7 31 DOUT8 30 29 DOUT9 28 LOCK 27 GND
PARALELL DATA OUT
VCC 220
10k
LOCK
1M
SERIAL DIGITAL INPUT
Fig. 11 Application Circuit - Unbalanced Serial Input Operation
VCC VCC VCC1 100n 10 10n 14 15 VCC 16 100n 17 75 75 18 19 100n 20 VCC 21 VCC 22 100n 23 475 24 VCC 25 26 2k VCC
1M
GND
SSI-CD 220 13 12 11 10 9 8 7 6 H RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 RSVD0 GND 100n 543 RSVD0 RSVD0 RSVD0 2 RSVD0 1 GND VCC 100n CD
GND GND C1 C2 VCC1 SDI SDI VCC2 RSVD0 GND EQ RSVD1 GND GND
SERIAL DIGITAL INPUT 10n 75 10n 37.5
VCC 75 75 VCC
10n
AGC VCC DIN DIN GND VCC
AGC CD DOUT DOUT CD-ADJ OEM
GND TRISTATE
GND 52 GND 51 RSVD1 50 RSVD1 49 48 V
CC3
10k VCC MODE
GS7005
10n
GS9024 VCC 10n
DOUT9
DOUT8
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
LOCK
DOUT0
CD 47 46 SMPTE 45 RSVD0 44 RSVD0 43 PCLKOUT 42 VDD 41 GND 40 GND GND
33 PCLK OUT
75 OUTPUT EYE MONITOR 1
475
220 LOCK
27 28 29 30 31 32 33 34 35 36 37 38 39 10k
10p
10n
PARALLEL DATA OUTPUTS
RSVD = Reserved. All resistors in ohms, all capacitors in farads, unless otherwise shown.
VCC
100n
Fig. 12 Typical Application Circuit with External Equalizer
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PACKAGE DIMENSIONS
17.20 BSC 14.00 BSC
14 2
0.40 MIN 0.13 MIN 0 MIN RADIUS 7 MAX 0 MIN
17.20 BSC 14.00 BSC
2.7 14 2 0.13 MIN. RADIUS 1.60 REF 0.88 0.15
GS7005
1.00 BSC
0.50 MAX 0.35 MIN
2.67 0.08 0.18 0.05
3.00 MAX
0.25 MAX 0.10 MIN
All dimensions are in millimetres. 52 pin MQFP BSC = Basic or nominal
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
REVISION NOTES: Added label to package dimension drawing to show package thickness and included the third view; Added information to section 5, PLL, MUX and f/10; Removed Figures 5 and 6 "Data to Follow"; Added resistor to Figures 11 and 12; Added to Package Dimensions legend.
For the latest product information, visit www.gennum.com.
GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
GENNUM CORPORATION
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright November 1999 Gennum Corporation. All rights reserved. Printed in Canada.
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